Conventionally, a fine circuit pattern and so on has been formed by performing an etching process such as a plasma etching on a substrate such as a semiconductor wafer, in a manufacturing process of a semiconductor device and so on. An etching mask is formed by a photolithography process using a photoresist, in such an etching process flow.
Various technologies have been developed to correspond to miniaturization of the pattern to be formed in the photolithography process as stated above. As one of these technologies, there is so-called a double patterning. This double patterning is the one enabling a formation of an etching mask with finer interval compared to a case when the etching mask is formed by one time patterning, by performing a two-stage patterning of a first mask pattern forming step and a second mask pattern forming step performed after the first mask pattern forming step (for example, refer to Patent Reference 1).
Patent Citation 1: Patent 2007-027742(KOKAI)